First-in, First-out (FIFO) memories are commonly used to transfer data between computer processors that operate relatively fast and peripheral equipment that operate relatively slow. Examples of such FIFO memories, and related control circuitry, are contained in the following United States Patents of inventor Ward, herein, and Kenneth L. Williams assigned to Texas Instruments Incorporated: U.S. Pat. No. 5,097,442 "Programmable Depth First-In, First-out Memory" issued application Ser. No. 03/17/92; U.S. Pat. No. 5,084,841 "Programmable Status Flag Generator FIFO Using Gray Code" issued application Ser. No. 01/28/92; U.S. Pat. No. 4,864,543 "First-In, First-Out Memory With Counter Address Pointers For Generating Multiple Memory Status Flags" issued application Ser. No. 09/05/89; U.S. Pat. No. 4,829,475 "Method and Apparatus For Simultaneous Address Increment and Memory Write Operations" issued application Ser. No. 05/09/89; and, U.S. Pat. No. 4,839,866 "Cascadable First-In, First-Out Memory" issued Jun. 13, 1989. Other examples of FIFO memories and related circuitry are also contained in the following United States patents assigned to Texas Instruments Incorporated: U.S. Pat. No. 5,117,395 "Expansible FIFO Memory For Accommodating Added Memory Stages in A Multistage Memory With Common Control Signals" of Hashimoto issued application Ser. No. 05/26/92; U.S. Pat. No. 4,933,901 "Method For Assigning Priority to Read and Write Requests Received Closely In Time" of Tai and Chiu issued Jun. 12, 1990; U.S. Pat. No. 4,815,039 "Fast Real-Time Arbiter" of Tai and Chiu issued Mar. 21, 1989; and, U.S. Pat. No. 4,882,710 "FIFO Memory Including Dynamic Memory Elements" of Hashimoto et al. issued Nov. 21, 1989. U.S. Pat. No. 4,868,784 "Microcomputer With A Multi-Channel Serial Port having a Single Port Address" of Marshall et al. issued Aug. 19, 1989 additionally assigned to Texas Instruments Incorporated incorporates a FIFO memory into the serial port of a microcomputer in aiding data transmission.
While the above patents provide important contributions to FIFO memories, further improvements are desirable. For example, it would be beneficial if the operating frequency of the FIFO could be increased. This would advantageously allow faster data output from the FIFO memory. It would be desirable to avoid having to address every single bit when performing a WRITE/READ operation. This would advantageously reduce the number of address pointers on the FIFO and thus save chip area.
The above advantages are provided by the invention herein. Other advantages will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.